AMD-K6 Datasheet, PDF (188/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
Table 26. Register State After RESET (continued)
Register
State (hex)
Notes
CR3
0000_0000h
CR4
0000_0000h
DR7
0000_0400h
DR6
FFFF_0FF0h
DR3
0000_0000h
DR2
0000_0000h
DR1
0000_0000h
DR0
0000_0000h
MCAR
0000_0000_0000_0000h
3
MCTR
0000_0000_0000_0000h
3
TR12
0000_0000_0000_0000h
3
TSC
0000_0000_0000_0000h
3
WHCR
0000_0000_0000_0000h
3
Notes:
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.
If EAX is non-zero, BIST failed.
2. EDX contains the AMD-K6 processor signature, where X indicates the processor Stepping ID.
3. The contents of these registers are preserved following the recognition of INIT.
4. The CD and NW bits of CR0 are preserved following the recognition of INIT.
7.4
State of Processor After INIT
The recognition of the assertion of INIT causes the processor to
empty its pipelines, to initialize most of its internal state, and to
branch to address FFFF_FFF0h—the same instruction
execution starting point used after RESET. Unlike RESET, the
processor preserves the contents of its caches, the
floating-point state, the MMX state, MSRs, and the CD and NW
bits of the CR0 register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
170
Power-on Configuration and Initialization
Chapter 7