AMD-K6 Datasheet, PDF (34/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
decoded simultaneously by the second short decoder along with
an ESC instruction decode in the first short decoder.
All of the MMX instructions, with the exception of the EMMS
instruction, are hardware decoded as short decodes. The MMX
instruction decode generates a RISC86 MMX operation and,
optionally, an associated MMX load or store operation. MMX
instruction decode is only allowed in the first short decoder.
However, instructions other than MMX and ESC instructions
can be decoded simultaneously by the second short decoder
along with an MMX instruction decode in the first short
decoder.
2.5
Centralized Scheduler
The scheduler is the heart of the AMD-K6 processor (see Figure
5 on page 17). It contains the logic necessary to manage
out-of-order execution, data forwarding, register renaming,
simultaneous issue and retirement of multiple RISC86
operations, and speculative execution. The scheduler’s buffer
can hold up to 24 RISC86 operations. This equates to a maximum
of 12 x86 instructions. When possible, the scheduler can
simultaneously issue a RISC86 operation to any available
execution unit (store, load, branch, integer, integer/multimedia,
or floating-point). In total, the scheduler can issue up to six and
retire up to four RISC86 operations per clock.
The main advantage of the scheduler and its operation buffer is
the ability to examine an x86 instruction window equal to 12
x86 instructions at one time. This advantage is due to the fact
that the scheduler operates on the RISC86 operations in
parallel and allows the AMD-K6 processor to perform dynamic
on-the-fly instruction code scheduling for optimized execution.
Although the scheduler can issue RISC86 operations for
out-of-order execution, it always retires x86 instructions in
order.
16
Internal Architecture
Chapter 2