AMD-K6 Datasheet, PDF (55/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Model-Specific
Registers (MSR)
63
Preliminary Information
AMD-K6^® Processor Data Sheet
The AMD-K6 processor provides five MSRs. The value in the
ECX register selects the MSR to be addressed by the RDMSR
and WRMSR instructions. The values in EAX and EDX are used
as inputs and outputs by the RDMSR and WRMSR instructions.
Table 5 lists the MSRs and the corresponding value of the ECX
register. Figures 28 through 32 show the MSR formats.
Table 5. Model-Specific Registers (MSRs)
Model-Specific Register
Value of ECX
Machine Check Address Register (MCAR)
00h
Machine Check Type Register (MCTR)
01h
Test Register 12 (TR12)
0Eh
Time Stamp Counter (TSC)
10h
Write Handling Control Register (WHCR) C000_0082h
For more information about the RDMSR and WRMSR
instructions, see the AMD K86™ Family BIOS and Software Tools
Development Guide, order# 21062.
MCAR and MCTR. The AMD-K6 processor does not support the
generation of a machine check exception. However, the
processor does provide a 64-bit Machine Check Address
Register (MCAR), a 64-bit Machine Check Type Register
(MCTR), and a Machine Check Enable (MCE) bit in CR4.
Because the processor does not support machine check
exceptions, the contents of the MCAR and MCTR are only
affected by the WRMSR instruction and by RESET being
sampled asserted (where all bits in each register are reset to 0).
0
MCAR
Figure 28. Machine-Check Address Register (MCAR)
Chapter 3
Software Environment
37