AMD-K6 Datasheet, PDF (60/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
Paging
The AMD-K6 processor can address up to 4 Gbytes of memory.
This memory can be segmented into pages. The size of these
pages is determined by the operating system design and the
values set up in the Page Directory Entries (PDE) and Page
Table Entries (PTE). The processor can access both 4-Kbyte
pages and 4-Mbyte pages, and the page sizes can be intermixed
within a page directory. When the Page Size Extension (PSE)
bit in CR4 is set, the processor translates linear addresses using
either the 4-Kbyte Translation Lookaside Buffer (TLB) or the
4-Mbyte TLB, depending on the state of the page size (PS) bit in
the page directory entry. Figures 35 and 36 show how 4-Kbyte
and 4-Mbyte page translations work.
Page
Page
Directory
Table
4-Kbyte
Page
Frame
PTE
PDE
CR3
31
22 21
Page Directory
Offset
Figure 35. 4-Kbyte Paging Mechanism
Page Table
Offset
12 11
Linear Address
Physical
Address
0
Page
Offset
42
Software Environment
Chapter 3