AMD-K6 Datasheet, PDF (56/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
63
54
0
MCTR
Reserved
Figure 29. Machine-Check Type Register (MCTR)
Test Register 12 (TR12). Test register 12 provides a method for
disabling the L1 caches. Figure 30 shows the format of TR12.
63
43 2 1 0
C
I
Reserved
Symbol Description Bit
CI Cache Inhibit Bit 3
Figure 30. Test Register 12 (TR12)
Time Stamp Counter. Wi t h e a ch p ro c e s s o r c l o ck cy c l e , t h e
processor increments the 64-bit time stamp counter (TSC) MSR.
Figure 31 shows the format of the TSC.
63
0
TSC
Figure 31. Time Stamp Counter (TSC)
38
Software Environment
Chapter 3