AMD-K6 Datasheet, PDF (200/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
pipelined cycles. The burst read cycles do not occur
back-to-back (wait states occur) if the processor is not ready to
start a new cycle, if higher priority data read or write requests
exist, or if NA# (next address) was sampled negated. Wait states
can also exist between burst cycles if the processor samples
AHOLD or BOFF# asserted.
8.9
Cache States
Table 30 shows all the possible cache-line states before and
after program-generated accesses to individual cache lines. The
table includes the correspondence between MESI states and
writethrough or writeback states for lines in the data cache.
Table 30. Data Cache States for Read and Write Accesses
Cache State After Access
Type
Cache State Before
Access
Access
Type¹
MESI State
Writeback
Writethrough State
invalid
single read
invalid
–
Cache
Read
Read Miss
Read
Hit
invalid
shared
exclusive
modified
burst read²
(cacheable)
–
–
–
shared or
exclusive³
shared
exclusive
modified
writethrough or
writeback³
writethrough
writeback
writeback
Write Miss
invalid
single write⁴
invalid
–
Cache
Write
Write Hit
shared
cache update and
single write
shared or
exclusive³
writethrough or
writeback³
exclusive or modified
cache update
modified
writeback
Notes:
1. Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32-byte burst read.
2. If CACHE# is driven Low and KEN# is sampled asserted.
3. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state.
4. A write cycle occurs only if the write allocate conditions as specified in “Write Allocate” on page 177 are not met.
– Not applicable or none.
182
Cache Organization
Chapter 8