AMD-K6 Datasheet, PDF (32/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
Instruction Decode
The AMD-K6 processor decode logic is designed to decode
multiple x86 instructions per clock (see Figure 4). The decode
logic accepts x86 instruction bytes and their predecode bits
from the instruction buffer, locates the actual instruction
boundaries, and generates RISC86 operations from these x86
instructions.
RISC86 operations are fixed-format internal instructions. Most
RISC86 operations execute in a single clock. RISC86 operations
are combined to perform every function of the x86 instruction
set. Some x86 instructions are decoded into as few as zero
RISC86 opcodes — for instance a NOP — or one RISC86
operation — a register-to-register add. More complex x86
instructions are decoded into several RISC86 operations.
Instruction Buffer
On-Chip ROM
Short Decoder #1
Short Decoder #2
Long Decoder
Vector Decoder
RISC86^® Sequencer
Vector Address
Figure 4. AMD-K6^® Processor Decode Logic
14
Internal Architecture
4 RISC86 Operations
Chapter 2