AMD-K6 Datasheet, PDF (264/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
16.6
Input Setup and Hold Timings for 66-MHz Bus Operation
Table 50. Input Setup and Hold Timings for 66-MHz Bus Operation
Symbol
Parameter Description
Preliminary Data
Min
Max
Figure
Comments
t₄₄ A[31:5] Setup Time
6.0 ns
86
t₄₅ A[31:5] Hold Time
1.0 ns
86
t₄₆
A20M# Setup Time
5.0 ns
86
Note 1
t₄₇
A20M# Hold Time
1.0 ns
86
Note 1
t₄₈
AHOLD Setup Time
5.5 ns
86
t₄₉
AHOLD Hold Time
1.0 ns
86
t₅₀
AP Setup Time
5.0 ns
86
t₅₁
AP Hold Time
1.0 ns
86
t₅₂
BOFF# Setup Time
5.5 ns
86
t₅₃
BOFF# Hold Time
1.0 ns
86
t₅₄
BRDY# Setup Time
5.0 ns
86
t₅₅
BRDY# Hold Time
1.0 ns
86
t₅₆ BRDYC# Setup Time
5.0 ns
86
t₅₇
BRDYC# Hold Time
1.0 ns
86
t₅₈ D[63:0] Read Data Setup Time
2.8 ns
86
t_{59 D[63:0] Read Data Hold Time}
1.5 ns
86
t₆₀ DP[7:0] Read Data Setup Time
2.8 ns
86
t₆₁
DP[7:0] Read Data Hold Time
1.5 ns
86
t₆₂
EADS# Setup Time
5.0 ns
86
t₆₃
EADS# Hold Time
1.0 ns
86
t₆₄
EWBE# Setup Time
5.0 ns
86
t₆₅
EWBE# Hold Time
1.0 ns
86
t₆₆ FLUSH# Setup Time
5.0 ns
86
Note 2
t₆₇
FLUSH# Hold Time
1.0 ns
86
Note 2
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
246
Signal Switching Characteristics
Chapter 16