AMD-K6 Datasheet, PDF (153/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
Misaligned I/O Read
and Write
Table 22 shows the misaligned I/O read and write cycle order
executed by the AMD-K6. In Figure 50, the least-significant
bytes (LSBs) are transferred first. Immediately after the
processor samples BRDY# asserted, it drives the second bus
cycle to transfer the most-significant bytes (MSBs) to complete
the misaligned bus cycle.
Table 22. Bus-Cycle Order During Misaligned I/O Transfers
Type of Access
I/O Read
I/O Write
First Cycle
LSBs
LSBs
Second Cycle
MSBs
MSBs
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
LOCK#
SCYC
D[63:0]
BRDY#
Misaligned I/O Read
Misaligned I/O Write
ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE
LSB
MSB
LSB
MSB
Figure 50. Misaligned I/O Transfer
Chapter 6
Bus Cycles
135