AMD-K6 Datasheet, PDF (116/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
5.23
Summary
Driven
HIT# (Inquire Cycle Hit)
Output
The processor asserts HIT# during an inquire cycle to indicate
that the cache line is valid within the processor’s instruction or
data cache (also known as a cache hit). The cache line can be in
the modified, exclusive, or shared state.
HIT # is always driven — except in Tri-State Test mode — and
only changes state the clock edge after the clock edge on which
EADS# is sampled asserted. It is driven in the same state until
the next inquire cycle.
5.24
Summary
Driven
HITM# (Inquire Cycle Hit To Modified Line)
Output
The processor asserts HITM # during an inquire cycle to
indicate that the cache line exists in the processor’s data cache
in the modified state. The processor performs a writeback cycle
as a result of this cache hit. If an inquire cycle hits a cache line
that is currently being written back, the processor asserts
HITM # but does not execute another writeback cycle. The
system logic must not expect the processor to assert ADS# each
time HITM # is asserted.
HITM# is always driven—except in Tri-State Test mode—and,
in particular, is driven to represent the result of an inquire cycle
the clock edge after the clock edge on which EADS # is sampled
asserted. If HITM # is negated in response to the inquire
address, it remains negated until the next inquire cycle. If
HITM# is asserted in response to the inquire address, it remains
asserted throughout the writeback cycle and is negated one
clock edge after the last BRDY # of the writeback is sampled
asserted.
98
Signal Descriptions
Chapter 5