AMD-K6 Datasheet, PDF (28/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
store predicted target addresses, special address ALUs
calculate target addresses on-the-fly during instruction decode.
The branch target cache augments predicted branch
performance by avoiding a one clock cache-fetch penalty. This
specialized target cache does this by supplying the first 16 bytes
of target instructions to the decoders when branches are
predicted. The return address stack is a unique device
specifically designed for optimizing CALL and RETURN pairs.
In summary, the AMD-K6 uses dynamic branch logic to
minimize delays due to the branch instructions that are
common in x86 software.
AMD-K6^® Processor Block Diagram. As shown in Figure 1 on page 11,
the high-performance, out-of-order execution engine of the
AMD-K6 processor is mated to a split level-one 64-Kbyte
writeback cache with 32 Kbytes of instruction cache and 32
Kbytes of data cache. The instruction cache feeds the decoders
and, in turn, the decoders feed the scheduler. The ICU issues
and retires RISC86 operations contained in the scheduler. The
system bus interface is an industry-standard 64-bit Pentium^®
processor demultiplexed bus.
The AMD-K6 processor combines the latest in processor
microarchitecture to provide the highest x86 performance for
t od ay’s p e rs ona l c o m p u t e rs. The A M D -K 6 of f e rs t ru e
sixth-generation performance and full x86 binary software
compatibility.
10
Internal Architecture
Chapter 2