AMD-K6 Datasheet, PDF (197/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
63
Reserved
Symbol
WCDE
WAELIM
WAE15M
Description
Bits
Always program to 0
8
Write Allocate Enable Limit
7–1
Write Allocate Enable 15-to-16-Mbyte 0
Note: Hardware RESET initializes this MSR to all zeros.
987
0
WAELIM
10
W
A
E
1
5
M
Figure 69. Write Handling Control Register (WHCR)
The WAELIM field is 7 bits wide. This field, multiplied by 4
Mbytes, defines an upper memory limit. Any pending write
cycle that addresses memory below this limit causes the
processor to perform a write allocate. Write allocate is disabled
for memory accesses at and above this limit unless the
processor determines a pending write cycle is cacheable by
means of one of the other write allocate mechanisms—Write to
a Cacheable Page and Write to a Sector. The maximum value of
this memory limit is ((2⁷ – 1) · 4 Mbytes) = 508 Mbytes. When all
the bits in this field are set to 0, all memory is above this limit
and this mechanism for allowing write allocate is effectively
disabled.
The Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit is
used to enable write allocations for the memory write cycles
that address the 1 Mbyte of memory between 15 Mbytes and 16
Mbytes. This bit must be set to 1 to allow write allocate in this
memory area. This bit is provided to account for a small number
of uncommon memory-mapped I/O adapters that use this
particular memory address space. If the system contains one of
these peripherals, the bit should be set to 0. The WAE15M bit is
ignored if the value in the WAELIM field is set to less than 16
Mbytes.
By definition a write allocate is never performed in the memory
area between 640 Kbytes and 1 Mbyte unless the processor
determines a pending write cycle is cacheable by means of one
of the other write allocate mechanisms—Write to a Cacheable
Page and Write to a Sector. It is not considered safe to perform
Chapter 8
Cache Organization
179