AMD-K6 Datasheet, PDF (259/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
16
16.1
Signal Switching Characteristics
The AMD-K6 processor signal switching characteristics are
presented in Table 47 through Table 55. Valid delay, float,
setup, and hold timing specifications are listed. These
specifications are provided for the system designer to
determine if the timings necessary for the processor to
interface with the system logic are met. Table 47 and Table 48
contain the switching characteristics of the CLK input. Table
49 through Table 52 contain the timings for the normal
operation signals. Table 53 contains the timings for RESET and
the configuration signals. Table 54 and Table 55 contain the
timings for the test operation signals.
All signal timings provided are:
s Measured between CLK, TCK, or RESET at 1.5 V and the
corresponding signal at 1.5 V—this applies to input and out-
put signals that are switching from Low to High, or from
High to Low
s Based on input signals applied at a slew rate of 1 V/ns
between 0 V and 3 V (rising) and 3 V to 0 V (falling)
s Valid within the operating ranges given in “Operating
Ranges” on page 233
s Based on a load capacitance (C_L) of 0 pF
CLK Switching Characteristics
Table 47 and Table 48 contain the switching characteristics of
the CLK input to the AMD-K6 processor for 66-MHz and
60-MHz bus operation, respectively, as measured at the voltage
levels indicated by Figure 82.
The CLK Period Stability specifies the variance (jitter) allowed
between successive periods of the CLK input measured at 1.5
V. This parameter must be considered as one of the elements of
clock skew between the AMD-K6 and the system logic.
Chapter 16
Signal Switching Characteristics
241