AMD-K6 Datasheet, PDF (265/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
Table 50. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)
Symbol
Parameter Description
Preliminary Data
Min
Max
Figure
Comments
t₆₈
HOLD Setup Time
5.0 ns
86
t₆₉
HOLD Hold Time
1.5 ns
86
t₇₀ IGNNE# Setup Time
5.0 ns
86
Note 1
t₇₁
IGNNE# Hold Time
1.0 ns
86
Note 1
t₇₂
INIT Setup Time
5.0 ns
86
Note 2
t₇₃
INIT Hold Time
1.0 ns
86
Note 2
t₇₄
INTR Setup Time
5.0 ns
86
Note 1
t₇₅
INTR Hold Time
1.0 ns
86
Note 1
t₇₆
INV Setup Time
5.0 ns
86
t₇₇
INV Hold Time
1.0 ns
86
t₇₈
KEN# Setup Time
5.0 ns
86
t₇₉
KEN# Hold Time
1.0 ns
86
t₈₀
NA# Setup Time
4.5 ns
86
t₈₁
NA# Hold Time
1.0 ns
86
t₈₂
NMI Setup Time
5.0 ns
86
Note 2
t₈₃
NMI Hold Time
1.0 ns
86
Note 2
t₈₄
SMI# Setup Time
5.0 ns
86
Note 2
t₈₅
SMI# Hold Time
1.0 ns
86
Note 2
t₈₆ STPCLK# Setup Time
5.0 ns
86
Note 1
t_{87 STPCLK# Hold Time}
1.0 ns
86
Note 1
t₈₈ WB/WT# Setup Time
4.5 ns
86
t₈₉
WB/WT# Hold Time
1.0 ns
86
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
Chapter 16
Signal Switching Characteristics
247