AMD-K6 Datasheet, PDF (270/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
16.9
RESET and Test Signal Timing
Table 53. RESET and Configuration Signals (60-MHz and 66-MHz Operation)
Symbol
Parameter Description
Preliminary Data
Figure
Min Max
Comments
t₉₀ RESET Setup Time
5.0 ns
87
t₉₁ RESET Hold Time
1.0 ns
87
t₉₂ RESET Pulse Width, V_CC and CLK Stable
15 clocks
87
t₉₃ RESET Active After V_CC and CLK Stable
1.0 ms
87
t₉₄ BF[2:0] Setup Time
1.0 ms
87
Note 3
t_{95 BF[2:0] Hold Time}
2 clocks
87
Note 3
t₉₆ BRDYC# Hold Time
1.0 ns
87
Note 4
t_{97 BRDYC# Setup Time}
2 clocks
87
Note 2
t₉₈ BRDYC# Hold Time
2 clocks
87
Note 2
t_{99 FLUSH# Setup Time}
5.0 ns
87
Note 1
t₁₀₀ FLUSH# Hold Time
1.0 ns
87
Note 1
t_{101 FLUSH# Setup Time}
2 clocks
87
Note 2
t₁₀₂ FLUSH# Hold Time
2 clocks
87
Note 2
Notes:
1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET
is sampled negated.
2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
4. If RESET is driven synchronously, BRDYC# must meet the specified hold time relative to the negation of RESET.
252
Signal Switching Characteristics
Chapter 16