AMD-K6 Datasheet, PDF (186/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
7.2
RESET Requirements
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V_CC
reach specification. (See “CLK Switching Characteristics” on
page 241 for clock specifications. See “Electrical Data” on page
233 for V_CC specifications.)
During a warm reset while CLK and V_CC are within
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
7.3
State of Processor After RESET
Output Signals
Table 25 shows the state of all processor outputs and
bidirectional signals immediately after RESET is sampled
asserted.
Table 25. Output Signal State After RESET
Signal
A[31:3], AP
ADS#, ADSC#
APCHK#
BE[7:0]#
BREQ
CACHE#
D/C#
D[63:0], DP[7:0]
FERR#
HIT#
HITM#
State
Floating
High
High
Floating
Low
High
Low
Floating
High
High
High
Signal
HLDA
LOCK#
M/IO#
PCD
PCHK#
PWT
SCYC
SMIACT#
TDO
VCC2DET
W/R#
State
Low
High
Low
Low
High
Low
Low
High
Floating
Low
Low
Registers
Table 26 on page 169 shows the state of all architecture
registers and Model-Specific Registers (MSRs) after the
processor has completed its initialization due to the recognition
of the assertion of RESET.
168
Power-on Configuration and Initialization
Chapter 7