AMD-K6 Datasheet, PDF (125/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
5.36
PCD (Page Cache Disable)
Output
Summary
The processor drives PCD to indicate the operating system’s
specification of cacheability for the page being addressed.
System logic can use PCD to control external caching. If PCD is
asserted, the addressed page is not cached. If PCD is negated,
the cacheability of the addressed page depends upon the state
of CACHE# and KEN#.
Driven and Floated
The state of PCD depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
s In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CR0 set to 0):
PCD output = CD bit in CR0
s In Protected and Virtual-8086 modes while caching is
enabled (CD bit in CR0 set to 0) and paging is enabled (PG
bit in CR0 set to 1):
• For accesses to I/O space, page directory entries, and
other non-paged accesses:
PCD output = PCD bit in CR3
• For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PCD output = PCD bit in page directory entry
• For accesses to 4-Kbyte pages:
PCD output = PCD bit in page table entry
PCD is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
PCD is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
Chapter 5
Signal Descriptions
107