AMD-K6 Datasheet, PDF (67/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
3.2
Chapter 3
Instructions Supported by the AMD-K6^® Processor
This section documents all of the x86 instructions supported by
the AMD-K6 processor. The following tables show the
instruction mnemonic, opcode, modR/M byte, decode type, and
RISC86 operation(s) for each instruction. Tables 10 through 12
define the integer, floating-point, and MMX instructions,
respectively.
The first column in these tables indicates the instruction
mnemonic and operand types with the following notations:
s reg8—byte integer register defined by instruction byte(s) or
bits 5, 4, and 3 of the modR/M byte
s mreg8—byte integer register defined by bits 2, 1, and 0 of
the modR/M byte
s reg16/32—word and doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
s mreg16/32—word and doubleword integer register defined
by bits 2, 1, and 0 of the modR/M byte
s mem8—byte integer value in memory
s mem16/32—word or doubleword integer value in memory
s mem32/48—doubleword or 48-bit integer value in memory
s mem48—48-bit integer value in memory
s mem64—64-bit value in memory
s imm8—8-bit immediate value
s imm16/32—16-bit or 32-bit immediate value
s disp8—8-bit displacement value
s disp16/32—16-bit or 32-bit displacement value
s disp32/48—doubleword or 48-bit displacement value
s eXX—register width depending on the operand size
s mem32real—32-bit floating-point value in memory
s mem64real—64-bit floating-point value in memory
s mem80real—80-bit floating-point value in memory
s mmreg—MMX register
s mmreg1—MMX register defined by bits 5, 4, and 3 of the
modR/M byte
s mmreg2—MMX register defined by bits 2, 1, and 0 of the
modR/M byte
Software Environment
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