AMD-K6 Datasheet, PDF (174/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
Interrupt
Acknowledge
In response to recognizing the system’s maskable interrupt
(INTR), the processor drives an interrupt acknowledge cycle at
the next instru cti on boundary. Dur ing an inter rupt
acknowledge cycle, the processor drives a locked pair of read
cycles as shown in Figure 61 on page 157. The first read cycle is
not functional, and the second read cycle returns the interrupt
number on D[7:0] (00h–FFh). Table 23 shows the state of the
signals during an interrupt acknowledge cycle.
Table 23. Interrupt Acknowledge Operation Definition
Processor Outputs
D/C#
M/IO#
W/R#
BE[7:0]#
A[31:3]
D[63:0]
First Bus Cycle
Low
Low
Low
EFh
0000_0000h
(ignored)
Second Bus Cycle
Low
Low
Low
FEh (low byte enabled)
0000_0000h
Interrupt number expected from interrupt
controller on D[7:0]
The system logic can drive INTR either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. To ensure it
is recognized, INTR must remain asserted until an interrupt
acknowledge sequence is complete.
156
Bus Cycles
Chapter 6