AMD-K6 Datasheet, PDF (204/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
Cache Snooping
Table 32 shows the conditions under which snooping occurs in
the AMD-K6 processor and the resources that are snooped.
Table 32. Snoop Action
Snooping Action
Type of Event
Type of Access
Instruction
Cache
Data Cache
Inquire Cycle
System Logic
yes¹
yes¹
Read
Instruction ^Miss
–
yes²
Cache
Read
Hit
–
no
Read
Miss
yes³
–
Internal Snoop
Read
Data
Hit
no
–
Cache
Write
Miss
yes³
–
Write
Hit
no
–
Notes:
1. The processor’s response to an inquire cycle depends on the state of the INV input signal
and the state of the cache line as follows:
For the instruction cache, if INV is sampled negated, the line remains invalid or valid, but
if INV is sampled asserted, the line is invalidated.
For the data cache, if INV is sampled negated, valid lines remain in or transition to the
shared state, a modified data cache line is written back before the line is marked shared
(with HITM# asserted), and invalid lines remain invalid. For the data cache, if INV is
sampled asserted, the line is marked invalid. Modified lines are written back before
invalidation.
2. If an internal snoop hits a modified line in the data cache, the line is written back and
invalidated. Then the instruction cache performs a burst read from memory.
3. If an internal snoop hits a line in the instruction cache, the instruction cache line is
invalidated and the data-cache read or write is performed from memory.
– Not applicable.
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Cache Organization
Chapter 8