AMD-K6 Datasheet, PDF (29/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
Socket 7
Bus
Interface
Predecode
Logic
Level-One Instruction Cache
(32 KByte + Predecode)
Level-One Cache
Controller
Out-of-Order
Execution Engine
Six RISC86^®
Operation Issue
16-Byte Fetch
Dual Instruction Decoders
x86 to RISC86
Four RISC86
Decode
Scheduler
Buffer
(24 RISC86)
64-Entry ITLB
Branch Logic
(8192-Entry BHT)
(16-Entry BTC)
(16-Entry RAS)
Instruction
Control Unit
Load
Store
Integer X
Multimedia
Integer Y
Floating-Point
Branch
Unit
Unit
(Register) Unit
Unit
(Register) Unit
Unit
(Resolving) Unit
Store
Queue
Level-One Dual-Port Data Cache (32 KByte)
128-Entry DTLB
Figure 1. AMD-K6^® Processor Block Diagram
2.3
Cache
Cache, Instruction Prefetch, and Predecode Bits
The writeback level-one cache on the AMD-K6 processor is
organized as a separate 32-Kbyte instruction cache and a
32-Kbyte data cache with two-way set associativity. The cache
line size is 32 bytes and lines are prefetched from main memory
using an efficient pipelined burst transaction. As the
instruction cache is filled, each instruction byte is analyzed for
instruction boundaries using predecoding logic. Predecoding
annotates each instruction byte with information that later
enables the decoders to efficiently decode multiple instructions
simultaneously.
The processor cache design takes advantage of a sectored
organization (see Figure 2 on page 12). Each sector consists of
64 bytes configured as two 32-byte cache lines. The two cache
lines of a sector share a common tag but have separate pairs of
MESI (Modified, Exclusive, Shared, Invalid) bits that track the
state of each cache line.
Chapter 2
Internal Architecture
11