AMD-K6 Datasheet, PDF (68/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
The second and third columns list all applicable opcode bytes.
The fourth column lists the modR/M byte when used by the
instruction. The modR/M byte defines the instruction as a
register or memory form. If modR/M bits 7 and 6 are documented
as mm (memory form), mm can only be 10b, 01b or 00b.
The fifth column lists the type of instruction decode — short,
long, and vector. The AMD-K6 decode logic can process two
short, one long, or one vector decode per clock.
The sixth column lists the type of RISC86 operation(s) required
for the instruction. The operation types and corresponding
execution units are as follows:
s load, fload, mload—load unit
s store, fstore, mstore—store unit
s alu—either of the integer execution units
s alux—integer X execution unit only
s branch—branch condition unit
s float—floating-point execution unit
s meu—multimedia execution unit for MMX software
s limm—load immediate, instruction control unit
Table 10. Integer Instructions
Instruction Mnemonic
AAA
AAD
AAM
AAS
ADC mreg8, reg8
ADC mem8, reg8
ADC mreg16/32, reg16/32
ADC mem16/32, reg16/32
ADC reg8, mreg8
ADC reg8, mem8
ADC reg16/32, mreg16/32
ADC reg16/32, mem16/32
ADC AL, imm8
First Second ModR/M Decode
Byte Byte
Byte
Type
RISC86^®
Opcodes
37h
vector
D5h 0Ah
vector
D4h 0Ah
vector
3Fh
vector
10h
11-xxx-xxx short alux
10h
mm-xxx-xxx long load, alux, store
11h
11-xxx-xxx short alu
11h
mm-xxx-xxx long load, alu, store
12h
11-xxx-xxx short alux
12h
mm-xxx-xxx short load, alux
13h
11-xxx-xxx short alu
13h
mm-xxx-xxx short load, alu
14h
xx-xxx-xxx short alux
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Software Environment
Chapter 3