AMD-K6 Datasheet, PDF (221/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
11
11.1
Test and Debug
The AMD-K6 processor implements various test and debug
modes to enable the functional and manufacturing testing of
systems and boards that use the processor. In addition, the
debug features of the processor allow designers to debug the
instruction execution of software components. This chapter
describes the following test and debug features:
s Built-In Self-Test (BIST)—The BIST, which is invoked after
the falling transition of RESET, runs internal tests that
exercise most on-chip RAM structures.
s Tri-State Test Mode—A test mode that causes the processor
to float its output and bidirectional pins.
s Boundary-Scan Test Access Port (TAP)—The Joint Test Action
Group (JTAG) test access function defined by the IEEE
Standard Test Access Port and Boundary-Scan Architecture
(IEEE 1149.1-1990) specification.
s Level-One (L1) Cache Inhibit—A feature that disables the
processor’s internal L1 instruction and data caches.
s Debug Support—Consists of all x86-compatible software
debug features, including the debug extensions.
Built-In Self-Test (BIST)
Following the falling transition of RESET, the processor
unconditionally runs its BIST. The internal resources tested
during BIST include the following:
s L1 instruction and data caches
s Instruction and Data Translation Lookaside Buffers (TLBs)
The contents of the EAX general-purpose register after the
completion of reset indicate if the BIST was successful. If EAX
contains 0000_0000h, then BIST was successful. If EAX is
non-zero, the BIST failed. Following the completion of the BIST,
the processor jumps to address FFFF_FFF0h to start
instruction execution, regardless of the outcome of the BIST.
The BIST takes approximately 295,000 processor clocks to
complete.
Chapter 11
Test and Debug
203