AMD-K6 Datasheet, PDF (107/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
5.12
Summary
Sampled
BRDYC# (Burst Ready Copy)
Input, Internal Pullup
BRDYC # has the identical function as BRDY #. In the event
BRDY # becomes too heavily loaded due to a large fanout or
loading in a system, BRDYC # can be used to reduce this
loading, which improves timing.
In addition, BRDYC # is sampled when RESET is negated to
configure the drive strength of A[20:3], ADS #, HITM #, and
W/R #. If BRDYC# is 0 during the falling transition of RESET,
these particular outputs are configured using higher drive
strengths than the standard strength. If BRDYC# is 1 during the
falling transition of RESET, the standard strength is selected.
BRDYC# is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS#.
BRDYC# is also sampled during the falling transition of RESET.
If RESET is driven synchronously, BRDYC # must meet the
specified hold time relative to the negation of RESET. If
RESET is driven asynchronously, the minimum setup and hold
time for BRDYC # relative to the negation of RESET is two
clocks.
Chapter 5
Signal Descriptions
89