AMD-K6 Datasheet, PDF (193/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
Table 29 describes how the CACHE# signal is driven based on
writeback cycles, the CI bit of TR12, unlocked memory reads,
and the PCD signal.
Table 29. CACHE# Signal Generation
Writeback
Cycle
1
0
0
0
0
0
0
0
0
CI Bit of TR12
X
1
0
1
0
1
0
1
0
Unlocked
Memory Reads
PCD Signal
X
X
1
High
1
High
0
High
0
High
1
Low
1
Low
0
Low
0
Low
CACHE#
Low
High
High
High
High
High
Low
High
High
Cache-Related Signals
Complete descriptions of the signals that control cacheability
and cache coherency are given on the following pages:
s CACHE#—page 90
s EADS#—page 94
s FLUSH#—page 97
s HIT#—page 98
s HITM#—page 98
s INV—page 102
s KEN#—page 103
s PCD—page 107
s PWT—page 109
s WB/WT#—page 116
8.4
Cache Disabling
To completely disable all cache accesses, the CD and NW bits
must be set to 1 and the cache must be completely flushed.
There are two different methods for flushing the cache. The
first method relies on the system logic and the second relies on
software.
Chapter 8
Cache Organization
175