AMD-K6 Datasheet, PDF (202/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
FLUSH#
WBINVD and INVD
Cache-Line
Replacement
s Instruction cache snoop during a data cache miss—The line in
the instruction cache is marked invalid, and the data-cache
read or write is performed from memory.
In response to sampling FLUSH# asserted, the processor writes
back any data cache lines that are in the modified state and
then marks all lines in the instruction and data caches as
invalid.
These x86 instructions cause all cache lines to be marked as
invalid. WBINVD writes back modified lines before marking all
cache lines invalid. INVD does not write back modified lines.
Replacing lines in the instruction or data cache, according to
the line replacement algorithms described in “Cache-Line
Fills” on page 176, ensures coherency between main memory
and the caches.
Table 31 on page 185 shows all possible cache-line states before
and after cache snoop or invalidation operations performed
with inquire cycles. This table shows all of the conditions for
writethroughs and writebacks to memory.
184
Cache Organization
Chapter 8