AMD-K6 Datasheet, PDF (134/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
5.52
Summary
Sampled
WB/WT# (Writeback or Writethrough)
Input
WB/WT#, together with PWT, specifies the data cache-line state
during cacheable read misses and write hits to shared cache
lines.
If WB/WT# = 0 or PWT = 1 during a cacheable read miss or write
hit to a shared cache line, the accessed line is cached in the
shared state. This is referred to as the writethrough state
because all write cycles to this cache line are driven externally
on the bus.
If WB/WT# = 1 and PWT = 0 during a cacheable read miss or a
write hit to a shared cache line, the accessed line is cached in
the exclusive state. Subsequent write hits to the same line
cause its state to transition from exclusive to modified. This is
referred to as the writeback state because the data cache can
contain modified cache lines that are subject to be written
back—referred as a writeback cycle—as the result of an inquire
cycle, an internal snoop, a flush operation, or the WBINVD
instruction.
WB/WT# is sampled on the clock edge that the first BRDY# or
NA# of a bus cycle is sampled asserted. If the cycle is a burst
read, WB/WT# is ignored during the last three assertions of
BRDY#. WB/WT# is sampled during memory read and
non-writeback write cycles and is ignored during all other types
of cycles.
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Signal Descriptions
Chapter 5