AMD-K6 Datasheet, PDF (164/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
AHOLD-Initiated
Inquire Hit to
Modified Line
Figure 56 on page 147 shows an AHOLD-initiated inquire cycle
that hits a modified line. During the inquire cycle in this
example, the processor asserts both HIT# and HITM# on the
clock edge after the clock edge that it samples EADS# asserted.
This condition indicates that the cache line exists in the
processor’s data cache in the modified state.
If the inquire cycle hits a modified line, the processor performs
a writeback cycle immediately after the inquire cycle to update
the modified cache line to shared memory (normally level-two
cache or DRAM). In Figure 56, the system logic holds AHOLD
asserted throughout the inquire cycle and the processor
writeback cycle. In this case, the processor is not driving the
address bus during the writeback cycle because AHOLD is
sampled asserted. The system logic writes the data to memory
by using its latched copy of the inquire cycle address. If the
processor samples AHOLD negated before it performs the
writeback cycle, it drives the writeback cycle by using the
address (A[31:5]) that it latched during the inquire cycle.
If INV is sampled asserted during an inquire cycle, the
processor transitions the line (if found) to the invalid state,
regardless of its previous state (the cache invalidation
operation is not visible on the bus). If INV is sampled negated
during an inquire cycle, the processor transitions the line (if
found) to the shared state. In either case, if the line is found in
the modified state, the processor writes it back to memory
before changing its state. Figure 56 shows that the processor
samples INV asserted during the inquire cycle and invalidates
the cache line after the inquire cycle.
146
Bus Cycles
Chapter 6