AMD-K6 Datasheet, PDF (199/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
5. Write to a Sector—A write allocate is performed if the
address of a pending write cycle matches the tag address of a
valid cache sector but the addressed cache line within the
sector is invalid. See “Write to a Sector” on page 178 for a
detailed description of this condition.
6. WCDE Bit—For proper functionality, always program bit 8
of WHCR to 0.
7. Less Than Limit (WAELIM)—The write allocate limit
mechanism determines if the memory area being addressed
is less than the limit set in the WAELIM field of WHCR. If
the address is less than the limit, write allocate for that
memory address is performed as long as conditions 9 and 10
do not prevent write allocate.
8. Between 640 Kbytes and 1 Mbyte —Write allocate is not
performed in the memory area between 640 Kbytes and 1
Mbyte. It is not considered safe to perform write allocations
between 640 Kbytes and 1 Mbyte (000A_0000h to
000F_FFFFh) because this area of memory is considered a
non-cacheable region of memory.
9. Between 15–16 Mbytes—If the address of a pending write
cycle is in the 1 Mbyte of memory between 15 Mbytes and 16
Mbytes, and the WAE15M bit is set to 1, write allocate for
this cycle is enabled.
10. Write Allocate Enable 15–16 Mbytes (WAE15M)—This
condition is associated with the Write Allocate Limit
mechanism and affects write allocate only if the limit
specified by the WAELIM field is greater than or equal to 16
Mbytes. If the memory address is between 15 Mbytes and 16
Mbytes, and the WAE15M bit in the WHCR is set to 0, write
allocate for this cycle is disabled.
8.8
Prefetching
The AMD-K6 processor performs instruction cache prefetching
for sector replacements only — as opposed to cache-line
replacements. The cache prefetching results in the filling of the
required cache line first, and a prefetch of the second cache line
making up the other half of the sector. Furthermore, the
prefetch of the second cache line is initiated only in the forward
direction—that is, only if the requested cache line is the first
position within the sector. From the perspective of the external
Chapter 8
Cache Organization
181