AMD-K6 Datasheet, PDF (12/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
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4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Page Directory Entry 4-Kbyte Page Table (PDE) . . . . . . . . . . . 44
Page Directory Entry 4-Mbyte Page Table (PDE) . . . . . . . . . . 44
Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Application Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 46
System Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Non-Pipelined Single-Transfer Memory Read/Write and
Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Misaligned Single-Transfer Memory Read and Write . . . . . . 129
Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . . 131
Burst Writeback due to Cache-Line Replacement . . . . . . . . . 133
Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Misaligned I/O Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Basic HOLD/HLDA Operation . . . . . . . . . . . . . . . . . . . . . . . . . 137
HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . 139
HOLD-Initiated Inquire Hit to Modified Line. . . . . . . . . . . . . 141
AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . . . . 143
AHOLD-Initiated Inquire Hit to Shared or
Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 147
AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
BOFF# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Basic Locked Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Locked Operation with BOFF# Intervention. . . . . . . . . . . . . . 155
Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . . . . 157
Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . . . . . . . 159
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Stop Grant and Stop Clock Modes, Part 1 . . . . . . . . . . . . . . . . 162
Stop Grant and Stop Clock Modes, Part 2 . . . . . . . . . . . . . . . . 163
INIT-Initiated Transition from Protected Mode to
Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 179
Write Allocate Logic Mechanisms and Conditions . . . . . . . . . 180
External Logic for Supporting Floating-Point
Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
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List of Figures