AMD-K6 Datasheet, PDF (229/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
Bypass Register (BR). The BR is a Test Data Register consisting of
a 1-bit shift register that provides the shortest path between
TDI and TDO. When the processor is not involved in a test
operation, the BR can be selected by an instruction to allow the
transfer of test data through the processor without having to
serially scan the test data through the BSR. This functionality
preserves the state of the BSR and significantly reduces test
time.
The BR register is selected by the BYPASS and HIGHZ
instructions as well as by any instructions not supported by the
AMD-K6.
TAP Instructions
The processor supports the three instructions required by the
IEEE 1149.1 standard — EXTEST, SAMPLE/PRELOAD, and
BYPASS — as well as two additional optional instructions —
IDCODE and HIGHZ.
Table 40 shows the complete set of TAP instructions supported
by the processor along with the 5-bit Instruction Register
encoding and the register selected by each instruction.
Table 40. Supported Tap Instructions
Instruction
Encoding
Register
Description
EXTEST¹
00000b
BSR
Sample inputs and drive outputs
SAMPLE / PRELOAD
00001b
BSR
Sample inputs and outputs, then load the BSR
IDCODE
00010b
DIR
Read DIR
HIGHZ
00011b
BR
Float outputs and bidirectional pins
BYPASS²
00100b–11110b
BR
Undefined instruction, execute the BYPASS instruction
BYPASS³
11111b
BR
Connect TDI to TDO to bypass the BSR
Notes:
1. Following the execution of the EXTEST instruction, the processor must be reset in order to return to normal, non-test operation.
2. These instruction encodings are undefined on the AMD-K6 processor and default to the BYPASS instruction.
3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open
during an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.
EXTEST. When the EXTEST instruction is execut ed, the
processor loads the BSR shift register with the current state of
the input and bidirectional pins in the Capture-DR state and
drives the output and bidirectional pins with the corresponding
values from the BSR output register in the Update-DR state.
Chapter 11
Test and Debug
211