AMD-K6 Datasheet, PDF (317/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
32 Test and Debug
32.1
32.2
The AMD-K6 processor implements various test and debug
modes to enable the functional and manufacturing testing of
systems and boards that use the processor. In addition, the
debug features of the processor allow designers to debug the
instruction execution of software components. This chapter
describes the following test and debug features of the AMD-K6
processor Model 7 that differ from those supported by the
AMD-K6 processor Model 6:
s Tri-State Test Mode—A test mode that causes the processor
to float its output and bidirectional pins.
s Boundary-Scan Test Access Port (TAP)—The Joint Test Action
Group (JTAG) test access function defined by the IEEE
Standard Test Access Port and Boundary-Scan Architecture
(IEEE 1149.1-1990) specification.
For more information about the test and debug modes of the
AMD-K6 processor Model 7, see Chapter 11, “Test and Debug”
on page 203.
Tri-State Test Mode
The VCC2DET, VCC2H/L#, and TDO signals are the only
outputs not floated in the Tri-State Test mode. VCC2DET and
VCC2H/L# must remain Low to ensure the system continues to
supply the specified processor core voltage to the V_CC2 pins.
TDO is never floated because the Boundary-Scan Test Access
Port must remain enabled at all times, including during the
Tri-State Test mode.
The Tri-State Test mode is exited when the processor samples
RESET asserted.
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard
that defines synchronous scanning test methods for complex
logic circuits, such as boards containing a processor. The
AMD-K6 processor supports the TAP standard defined in the
Chapter 32
Test and Debug
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