AMD-K6 Datasheet, PDF (192/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
The operating system can control the cacheability of a page.
The paging mechanism is controlled by CR3, the Page Directory
Entry (PDE), and the Page Table Entry (PTE). Within CR3,
PDE, and PTE are Page Cache Disable (PCD) and Page
Writethrough (PWT) bits. The values of the PCD and PWT bits
used in Table 27 through Table 29 are taken from either the PTE
or PDE. For more information see the descriptions of PCD and
PWT on pages 107 and 109, respectively.
Table 27 through Table 29 describe the logic that determines
the cacheability of a cycle and how that cacheability is affected
by the PCD bits, the PWT bits, the PG bit of CR0, the CD bit of
CR0, writeback cycles, the Cache Inhibit (CI) bit of Test
Register 12 (TR12), and unlocked memory reads.
Table 27 describes how the PWT signal is driven based on the
values of the PWT bits and the PG bit of CR0.
Table 27. PWT Signal Generation
PWT Bit* PG Bit of CR0
1
1
0
1
1
0
0
0
Note:
* PWT is taken from PTE or PDE
PWT Signal
High
Low
Low
Low
Table 28 describes how the PCD signal is driven based on the
values of the CD bit of CR0, the PCD bits, and the PG bit of
CR0.
Table 28. PCD Signal Generation
CD Bit of CR0 PCD Bit*
1
X
0
1
0
0
0
1
0
0
Note:
* PCD is taken from PTE or PDE
PG Bit of CR0
X
1
1
0
0
PCD Signal
High
High
Low
Low
Low
174
Cache Organization
Chapter 8