AMD-K6 Datasheet, PDF (222/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
11.2
Tri-State Test Mode
The Tri-State Test mode causes the processor to float its output
and bidirectional pins, which is useful for board-level
manufacturing testing. In this mode, the processor is
electrically isolated from other components on a system board,
allowing automated test equipment (ATE) to test components
that drive the same signals as those the processor floats.
If the FLUSH# signal is sampled Low during the falling
transition of RESET, the processor enters the Tri-State Test
mode. (See “FLUSH# (Cache Flush)” on page 97 for the
specific sampling requirements.) The signals floated in the
Tri-State Test mode are as follows:
s A[31:3]
s ADS#
s ADSC#
s AP
s APCHK#
s BE[7:0]#
s BREQ
s CACHE#
s D/C#
s D[63:0]
s DP[7:0]
s FERR#
s HIT#
s HITM#
s HLDA
s LOCK#
s M/IO#
s PCD
s PCHK#
s PWT
s SCYC
s SMIACT#
s W/R#
The VCC2DET and TDO signals are the only outputs not
floated in the Tri-State Test mode. VCC2DET must remain Low
to ensure the system continues to supply the specified
processor core voltage to the V_CC2 pins. TDO is never floated
because the Boundary-Scan Test Access Port must remain
enabled at all times, including during the Tri-State Test mode.
The Tri-State Test mode is exited when the processor samples
RESET asserted.
204
Test and Debug
Chapter 11