AMD-K6 Datasheet, PDF (214/346 Pages) Advanced Micro Devices – AMD-K6 Processor

AMD-K6^® Processor Data Sheet
Preliminary Information
20695H/0—March 1998
10.3
196
SMM State-Save Area
When the processor acknowledges an SMI# interrupt by
asserting SMIACT#, it saves its state in a 512-byte SMM
state-save area shown in Table 34. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
down to SMM base address + FE00h.
Table 34 shows the offsets in the SMM state-save area relative
to the SMM base address. The SMM service routine can alter
any of the read/write values in the state-save area.
Table 34. SMM State-Save Area Map
Address Offset
Contents Saved
FFFCh
CR0
FFF8h
CR3
FFF4h
EFLAGS
FFF0h
EIP
FFECh
EDI
FFE8h
ESI
FFE4h
EBP
FFE0h
ESP
FFDCh
EBX
FFD8h
EDX
FFD4h
ECX
FFD0h
EAX
FFCCh
DR6
FFC8h
DR7
FFC4h
TR
FFC0h
LDTR Base
FFBCh
GS
FFB8h
FS
FFB4h
DS
FFB0h
SS
FFACh
CS
FFA8h
ES
Notes:
— No data dump at that address
* Only contains information if SMI# is asserted during a valid I/O bus cycle.
System Management Mode (SMM)
Chapter 10