AMD-K6 Datasheet, PDF (301/346 Pages) Advanced Micro Devices – AMD-K6 Processor

20695H/0—March 1998
Preliminary Information
AMD-K6^® Processor Data Sheet
63
48 47
32 31
SYSRET CS Selector and SS
Selector Base
SYSCALL CS Selector and SS
Selector Base
0
Target EIP Address
Figure 103. SYSCALL/SYSRET Target Address Register (STAR)
Table 61. SYSCALL/SYSRET Target Address Register (STAR) Definition
Bit
Description
R/W
63–48 SYSRET CS and SS Selector Base
R/W
47–32 SYSCALL CS and SS Selector Base
R/W
31–0 Target EIP Address
R/W
24.2
Instructions Supported by the AMD-K6^® Processor
This section documents the x86 instructions supported by the
AMD-K6 processor Model 7 that are not supported by AMD-K6
processor Model 6. For information about the remaining x86
instructions supported by the AMD-K6 processor Model 6, see
Chapter 3, “Software Environment” on page 21.
Table 62 shows the instruction mnemonic, opcode, modR/M
byte, decode type, and RISC86 operation(s) for each
instruction. The first column of the tables indicates the
instruction mnemonic and operand types. The second and third
columns list all applicable opcode bytes. The fourth column
lists the modR/M byte when used by the instruction. The
modR/M byte defines the instruction as a register or memory
form. The fifth column lists the type of instruction decode —
short, long, and vector. The sixth column lists the type of
RISC86 operation(s) required for the instruction.
Table 62. Integer Instructions
Instruction Mnemonic
SYSCALL
SYSRET
First Second
Byte Byte
0Fh 05h
0Fh 07h
ModR/M
Byte
Decode
Type
vector
vector
RISC86^®
Opcodes
Chapter 24
Software Environment
283