LAN9420 Datasheet, PDF (98/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

4.2.9
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Power Management Control Register (PMT_CTRL)
Offset:
00E0h
Size:
32 bits
This register controls the wake event detection features. This register also controls the SCSR soft reset
to the PHY.
Note: If waking from a reduced-power state causes the assertion of a device reset, this register will
be cleared.
BITS
31:11
10
9
8
7:5
4:3
2:0
DESCRIPTION
RESERVED
PHY Reset (PHY_RST)
Writing a ‘1’ to this bit resets the PHY. The internal logic automatically holds
the PHY reset for a minimum of 100us. When the PHY is released from
reset, this bit is automatically cleared. All writes to this bit are ignored while
this bit is high.
Wake-On-Lan Wakeup Enable (WOL_EN)
When set, the MAC Wake Detect signal is enabled as a wake event and
will set the PME_STATUS in the PCI_PMCSR. The MAC Wake Detect
signal can be programmed for assertion upon detection of a Wakeup Frame
or Magic Packet.
Energy-Detect Wakeup Enable (ED_EN)
When set, the PHY Interrupt signal is enabled as a wake event and will set
the PME_STATUS bit in the PCI_PMCSR. The PHY interrupt can be
programmed for assertion upon detection of a link status change (Energy
Detect) event.
RESERVED
Wakeup Status (WUPS)
This field indicates the cause of the last wake event. This field is cleared
by writing ‘1’ to the currently set bit(s). WUPS is encoded as follows:
00b – No wakeup event detected
x1b – PHY interrupt (Energy-Detect)
1xb – MAC wakeup event (Wakeup Frame or Magic Packet)
Note: If waking from a reduced-power state causes the assertion of a
device reset, the wakeup status bits will be cleared.
RESERVED
TYPE
RO
SC
R/W
R/W
RO
R/WC
RO
DEFAULT
-
0b
0b
0b
-
00b
000b
Revision 1.6 (07-18-11)
98
DATASHEET
SMSC LAN9420/LAN9420i