LAN9420 Datasheet, PDF (165/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Table 5.11 PCI I/O Timing Values
SYMBOL
DESCRIPTION
MIN
t_val
PCICLK to signal valid delay - bussed signals
2
t_val(nREQ) PCICLK to nREQ signal valid delay (Note 5.15)
2
t_on
Float to active delay
2
t_off
Active to float delay
t_su
Input setup time to PCICLK - bussed signals
7
t_su(nGNT) nGNT input setup time to PCICLK (Note 5.15)
10
t_h
Input hold time from PCICLK
0
t_rst
PCInRST active time after power stable
(Note 5.16)
1
t_rst-clk
PCInRST active time after PCICLK stable
(Note 5.16)
100
t_rst-off
Rest active to output float delay (Note 5.16)
TYP
MAX
11
12
28
40
UNITS
ns
ns
ns
ns
ns
ns
ns
ms
us
ns
Note: PCI signal timing is specified with loads detailed in Section 4.2.3.2 of the PCI Local Bus
Specification, Rev. 3.0.
Note 5.15 nREQ and nGNT are point-to-point signals and have different timing characteristics than
bussed signals. All other signals are bussed.
Note 5.16 PCInRST is asserted and deasserted asynchronously with respect to the PCICLK signal.
SMSC LAN9420/LAN9420i
165
DATASHEET
Revision 1.6 (07-18-11)