LAN9420 Datasheet, PDF (83/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
4. Bit 0 of the Wakeup Status (WUPS[0]) in the Power Management Control Register (PMT_CTRL)
must be cleared since a set bit will cause the immediate assertion of wake event when ED_EN is
set. The WUPS[0] bit will not clear if the internal PHY interrupt is asserted.
5. Set the Energy-Detect Wakeup Enable (ED_EN) bit in the Power Management Control Register
(PMT_CTRL).
6. Set the PME Enable (PME_EN) bit in the PCI Power Management Control and Status Register
(PCI_PMCSR). Note that PME_EN must be set before entering the D3 state. If this bit is not set,
the internal PHY will be reset and placed in the General Power-Down state and the device will not
be able to detect an Ethernet link status change.
7. If the device is to be placed in the D3 state, set the Power Management State (PM_STATE) field
of the PCI Power Management Control and Status Register (PCI_PMCSR) to 11b (‘D3’ state). The
device will enter D3_HOT. Device behavior in this state is described in Section 3.7.4.4, "The D3HOT
State," on page 78.
On detection of Ethernet activity (energy), the device will assert the nPME signal. The nPME signal
will remain asserted until the PME Enable (PME_EN) and/or the PME Status (PME_STATUS) bits are
cleared by the Host.
SMSC LAN9420/LAN9420i
83
DATASHEET
Revision 1.6 (07-18-11)