LAN9420 Datasheet, PDF (49/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
BITS
10:0
Table 3.10 TDES1 Bit Fields (continued)
DESCRIPTION
TBS1 - Transmit Buffer 1 Size
Indicates the size, in bytes, of the first data buffer. If this field is 0, the DMA controller ignores this
buffer and uses buffer2.
Host Actions: Initializes this field.
DMAC Actions: Reads this field to determine the allocated size of associated data buffer.
Transmit Descriptor 2 (TDES2)
BITS
31:0
Table 3.11 TDES2 Bit Fields
DESCRIPTION
Buffer 1 Address Pointer
This is the physical address of buffer 1. There are no limitations on the buffer address alignment.
Host Actions: Initializes this field.
DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer
address.
Transmit Descriptor 3 (TDES3)
BITS
31:0
Table 3.12 TDES3 Bit Fields
DESCRIPTION
Buffer 2 Address Pointer (Next Descriptor Address)
The TCH (Second Address Chained) bit (TDES1[24]) determines the usage of this field as
follows:
TCH is zero: This field contains the pointer to the address of buffer 2 in Host memory. There
are no limitations on buffer address alignment.
TCH is one: Descriptor chaining is in use and this field contains the pointer to the next
descriptor in Host memory. The descriptor must be 4-DWORD (16-byte) aligned (TDES3[3:0] =
0000b). In the case where the buffer is not 4-DWORD aligned, the resulting behavior is
undefined.
Note: If TER (TDES1[25]) is set, TCH is ignored and this field is treated as a pointer to buffer
2 as in the “TCH is zero” case above.
Host Actions: Initializes this field.
DMAC Actions: Reads this field upon opening a new DMA descriptor to obtain the buffer
address.
SMSC LAN9420/LAN9420i
49
DATASHEET
Revision 1.6 (07-18-11)