LAN9420 Datasheet, PDF (154/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

4.6.2
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
PCI Power Management Control and Status Register (PCI_PMCSR)
Offset:
7Ch
Size:
32 bits
This register controls the device’s power state.
Note: The format of this register is equivalent to offsets 7:4 of the Power Management Register Block
Definition as described in Revision 1.1 of the PCI Bus Power Management Interface
Specification.
BITS
DESCRIPTION
31:24
23:16
15
14:13
12:9
8
7:2
Data (PM_DATA)
This field is not implemented and returns zeros.
PMCSR PCI to PCI Bridge Support Extensions (PMCSR_BSE)
This field is not implemented and returns zeros.
PME Status (PME_STATUS)
This bit is set when an enabled power management event has been
detected. Writing a “1” to this bit will clear it provided that the source of the
event has been cleared. This bit is level-triggered and will not clear on write
if the source of the power management event remains asserted. Writing a
“0” has no effect.
When the VAUXDET input pin is low, this bit is reset on assertion of a power-
on reset or PCI reset (PCInRST).
When the VAUXDET input pin is high, this bit is unaffected by assertion of
PCI reset (PCInRST). In this case, the bit will maintain its setting until
cleared with a write, or until assertion of a power-on reset.
Data Scale (DATA_SCALE)
This field is not implemented and returns zeros as a result of the PM_DATA
field of this register not being implemented.
Data Select (DATA_SELECT)
This field is not implemented and returns zeros as a result of the PM_DATA
field of this register not being implemented.
PME Enable (PME_EN)
When this bit is set, the device will assert the external nPME signal if the
PME Status (PME_STATUS) bit in this register is set. When this bit is
cleared, the device will not assert the external nPME signal.
When the VAUXDET input pin is cleared, this bit is reset on assertion of a
power-on reset or PCI reset (PCInRST).
When the VAUXDET input pin is set, this bit is unaffected by assertion of
PCI reset (PCInRST). In this case, the bit will maintain its setting until
cleared with a write, or until assertion of a power-on reset.
If PME_EN is cleared, the device will automatically place the PHY into
General Power-Down when entering the D3_HOT state.
RESERVED
TYPE
RO
RO
R/WC
RO
RO
R/W
RO
DEFAULT
00h
00h
Note 4.11
00b
0000b
Note 4.11
-
Revision 1.6 (07-18-11)
154
DATASHEET
SMSC LAN9420/LAN9420i