LAN9420 Datasheet, PDF(41/171 Page) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

LAN9420 Datasheet, PDF (41/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

◁

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

3.4.2.1

Receive Descriptors

The receive descriptors must be 4-DWORD (16-byte) aligned. Except for the case where descriptor

address chaining is disabled (RCH=0), there are no alignment restrictions on receive buffer addresses.

Providing two buffers, two byte-count buffers, and two address pointers in each descriptor facilitates

compatibility with various types of memory-management schemes. Figure 3.16 shows the receive

descriptor.

OW FF

ES DE R LE RF MF FS LS TL CS FT RW ME DB CE R

RDES0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED

RE RC RES

RBS2

RBS1

RDES1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUFFER 1 ADDRESS POINTER

RDES2

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUFFER 2 ADDRESS POINTER

RDES3

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure 3.16 Receive Descriptor

Receive Descriptor 0 (RDES0)

RDES0 contains the received frame status, the frame length, and the descriptor ownership information.

BITS

Table 3.5 RDES0 Bit Fields

DESCRIPTION

OWN - Own Bit

When set, indicates that the descriptor block and associated buffer(s) are owned by the DMA

controller. When reset, indicates that the descriptor block and associated buffer(s) are owned by

the Host system.

Host Actions: Checks this bit to determine ownership of the descriptor block and associated

buffer(s). The Host sets this bit to pass ownership to the DMAC. The Host does not modify a

descriptor block or access its associated buffer(s) until this bit is cleared by DMAC or until the

DMAC is in STOPPED state, whichever comes first.

DMAC Actions: Reads this bit to determine ownership of the descriptor block and its associated

buffer(s). The DMAC clears this bit either when it completes the frame reception or when the

buffers that are associated with this descriptor are full. By clearing this bit, the DMAC closes the

descriptor block and passes ownership to the Host. If the DMAC fetches a descriptor with the

OWN bit cleared, the DMAC state machine enters the SUSPENDED state.

FF - Filter Fail

Indicates that the current frame failed the receive address filtering. This bit can only be set when

receive all (RXALL) is set in the MAC control register (MAC_CR). This bit is only valid when the

last descriptor (LS) bit is set and the received frame is greater than or equal to 64 bytes in length.

Host Actions: Checks this bit to determine status.

DMAC Actions: Sets/clears this bit to define status.

SMSC LAN9420/LAN9420i

DATASHEET

Revision 1.6 (07-18-11)

▷