LAN9420 Datasheet, PDF (76/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

3.7.4
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
XI input pin with a single-ended 25MHz clock source. If a single-ended source is selected, the clock
input must run continuously for normal device operation.
Internally, LAN9420/LAN9420i generates its required clocks with a phase-locked loop (PLL). The
LAN9420/LAN9420i reduces its power consumption in the D3 state by disabling its internal PLL and
derivative clocks. The 25MHz clock remains operational in all states where power is applied.
Please refer to Section 5.9, "Clock Circuit," on page 167 for more information on clock requirements.
Power States
This section describes the operation of LAN9420/LAN9420i in each device power state (‘D’ states) as
well as the events required to cause state transitions. LAN9420/LAN9420i’s behavior is dependant on
the device’s VAUXDET pin (the device’s ability to detect wake events in D3_COLD). Specific behaviors
are discussed in the sections that follow.
Device power states and associated state transitions are illustrated in Figure 3.28 below. Note that
Figure 3.28 includes the system’s mechanical off (G3) power state for illustrative purposes. This is the
G3 state as defined by the ACPI specification. In this state all power (+3.3V and 3.3Vaux) is off.
T7
D0_A
T2
T11
T3
T1
T5,
T8
D0_U
T9 T10
D3_HOT
T4
D3_COLD
T6
G3
T12 Vaux Off
Figure 3.28 LAN9420/LAN9420i Device Power States
Some power state transitions may place the PHY in the General Power-Down state as noted in the
sections that follow. Please refer to Section 3.6.8.1, "General Power-Down," on page 73 for more
information on this mode of operation.
3.7.4.1
3.7.4.1.1
3.7.4.1.2
G3 State (Mechanical Off)
G3 is not a device power state, but is discussed here for illustrative purposes. In the G3 state all PCI
power is off. In this state all device context is lost.
POWER MANAGEMENT EVENTS IN G3
LAN9420/LAN9420i does not detect power management events in the G3 state.
EXITING THE G3 STATE
When the system leaves the G3 state, the device will behave as follows. State transitions are illustrated
in Figure 3.28 on page 76.
Revision 1.6 (07-18-11)
76
DATASHEET
SMSC LAN9420/LAN9420i