LAN9420 Datasheet, PDF (125/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
4.4.3 MAC Address Low Register (ADDRL)
Offset:
0088h
Size:
32 bits
This register contains the lower 32 bits of the physical address of the MAC, where ADDRL[7:0] is the
first octet of the Ethernet frame.
BITS
31:0
DESCRIPTION
Physical Address [31:0]
This field contains the lower 32 bits (32:0) of the Physical Address of this
MAC device.
TYPE
R/W
DEFAULT
32‘hF
Table 4.6 below illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the
reception of the Ethernet physical address.
Table 4.6 ADDRL, ADDRH Byte Ordering
ADDRL, ADDRH
ADDRL[7:0]
ADDRL[15:8]
ADDRL[23:16]
ADDRL[31:24]
ADDRH[7:0]
ADDRH[15:8]
ORDER OF RECEPTION ON ETHERNET
1^st
2^nd
3^rd
4^th
5^th
6^th
As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and
ADDRH registers would be programmed as shown in Figure 4.2. The values required to automatically
load this configuration from the EEPROM are shown in Section 3.3.5.1, "EEPROM Format," on
page 31.
31 24 23 16 15 8 7 0
xx
xx
0xBC 0x9A
ADDRH
31 24 23 16 15 8 7
0
0x78 0x56 0x34 0x12
ADDRL
Figure 4.2 Example ADDRL, ADDRH Address Ordering
SMSC LAN9420/LAN9420i
125
DATASHEET
Revision 1.6 (07-18-11)