LAN9420 Datasheet, PDF(112/171 Page) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

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LAN9420 Datasheet, PDF (112/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

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4.3.7

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Datasheet

DMA Controller Control (Operation Mode) Register (DMAC_CONTROL)

Offset:

0018h

Size:

32 bits

This register establishes the RX and TX operating modes and commands. This should be the last

DCSR written as part of initialization.

BITS

31:23

RESERVED

DESCRIPTION

TYPE

R/W

DEFAULT

21 Must Be One (MBO)

This bit must be set to â1â for normal device operation.

R/W

19:16

15:14

RESERVED

R/W

00b

13 Start/Stop Transmission Command (ST)

R/W

When set, the transmission process is placed in the Running state, and the

DMAC checks the transmit list at the current position for a frame to be

transmitted.

Descriptor acquisition is attempted either from the current position in the list,

which is the transmit list base address set by TX_BASE_ADDR, or from the

position retained when the transmit process was previously stopped. If no

descriptor can be acquired, the transmit process enters the Suspended

state. If the current descriptor is not owned by the DMA Controller, the

transmission process enters the Suspended state and the Transmit Buffer

Unavailable (DMAC_STATUS bit [2]) is set. The Start Transmission

command is effective only when the transmission process is stopped. If the

command is issued before setting the TX_BASE_ADDR, then the DMA

Controllerâs behavior will be undefined.

When reset, the transmission process is placed in the Stopped state after

completing the transmission of the current frame. The next descriptor

position in the transmit list is saved, and becomes the current position when

transmission is restarted.

The Stop Transmission command is effective only when the transmission

process is in either Running or Suspended state.

12:3 RESERVED

Operate on Second Frame (OSF)

R/W

When set, this bit instructs the DMA Controller to process a second frame

of transmit data even before status for the first frame is obtained. This bit

affects the DMA Controller but not the MIL.

Revision 1.6 (07-18-11)

112

DATASHEET

SMSC LAN9420/LAN9420i

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