LAN9420 Datasheet, PDF (80/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
„ Software Reset (SRST): This reset is initiated by setting the Software Reset (SRST) bit in the Bus
Mode Register (BUS_MODE). Software Reset does not clear control register bits marked as NASR.
„ PHY Reset via PMT_CTRL (PHY_RST): This reset is asserted by setting the PHY Reset
(PHY_RST) in the Power Management Control Register (PMT_CTRL). Refer to section Section
3.6.9.1, "PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)," on page 74 for more information.
„ PHY Soft Reset (PHY_SRST): This reset is asserted by writing a ‘1’ to bit 15 of the PHY’s Basic
Control Register. Refer to section Section 3.6.9.2, "PHY Soft Reset via PHY Basic Control Register
bit 15 (PHY Reg. 0.15)," on page 74 for more information.
The reset map in Table 3.22 shows the conditions under which various modules within
LAN9420/LAN9420i are reset.
BLOCK
PCI PME Logic
PHY
(Note 3.11)
EEPROM Load
PCI Configuration
Registers
(except PME registers)
MAC
TX/RX DMACS
SCSR
POR
X
X
X
X
X
X
X
Table 3.22 Reset Map
PCInRST
Note 3.6
X
D3RST
Note 3.8
X
X
X
(Note 3.9)
SRST
PHY_RST PHY_SRST
X
X
(Note 3.10)
X
X
X
X
X
X
X
X
X
(Note 3.7)
3.7.5.1
Note 3.6
Note 3.7
PME logic is reset by PCInRST if LAN9420/LAN9420i is not configured to support D3_COLD
wake; PME logic is not reset by PCInRST if LAN9420/LAN9420i is configured to support
D3_COLD wake.
Software Reset does not clear control register bits marked as NASR.
Note 3.8
Note 3.9
If PHY was reset on entry to the D3_HOT, it will be reset when exiting the D3_HOT. If the PHY
was not reset on entry to the D3_HOT, it will not be reset when exiting D3_HOT.
The Subsystem Vendor ID (SSVID) Subsystem Device ID (SSID) registers (optionally
loaded from the EEPROM) are not reset during this transition.
Note 3.10 PHY register bits designated as NASR are not initialized by setting the PHY Soft Reset bit
in the PHY’s Basic Control Register.
Note 3.11 PHY reset conditions and mode settings are discussed in Section 3.7.5.1, "PHY Resets,"
on page 80
PHY Resets
In addition to the PHY_RST, PHY_SRST and PCInRST noted in Table 3.22, the PHY may also be reset
on specific state transitions depending on the state of the VAUXDET signal and PME Enable
(PME_EN) bit in the PCI Power Management Control and Status Register (PCI_PMCSR). Resets may
leave the PHY in normal operating mode (all-capable with auto-negotiation enabled) or in the General
Power-Down mode. Specific PHY reset conditions and the state of the PHY following reset, are
Revision 1.6 (07-18-11)
80
DATASHEET
SMSC LAN9420/LAN9420i