LAN9420 Datasheet, PDF (163/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
5.6 PCI Clock Timing
The following specifies the PCI clock requirements for LAN9420/LAN9420i:
0.5*VDD33IO
0.4*VDD33IO
0.3*VDD33IO
PCICLK
t_cyc
t_high
t_low
0.6*VDD33IO
0.2*VDD33IO
Figure 5.2 PCI Clock Timing
0.4*VDD33IO p-to-p
(minimum)
Table 5.9 PCI Clock Timing Values
SYMBOL
t_cyc
t_high
t_low
-
DESCRIPTION
PCICLK cycle time
PCICLK high time
PCICLK low time
PCICLK slew rate (Note 5.14)
MIN
TYP
30
11
11
1
MAX
∞
4
UNITS
ns
ns
ns
V/ns
Note 5.14 This slew rate must be met across the minimum peak-to-peak portion of the clock
waveform as shown in Figure 5.2.
SMSC LAN9420/LAN9420i
163
DATASHEET
Revision 1.6 (07-18-11)