LAN9420 Datasheet, PDF (166/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

5.8
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
EEPROM Timing
The following specifies the EEPROM timing requirements for LAN9420/LAN9420i:
EECS
EECLK
EEDO
EEDI
EEDI (VERIFY)
t_cshckh
t_ckcyc
t_ckh t_ckl
t_dvckh t_ckhdis
t_dsckh
t_dhckh
t_cshdv
t_csl
t_cklcsl
t_ckldis
t_dhcsl
Figure 5.4 EEPROM Timing
SYMBOL
t_ckcyc
t_ckh
t_ckl
t_cshckh
t_cklcsl
t_dvckh
t_ckhdis
t_dsckh
t_dhckh
t_ckldis
t_cshdv
t_dhcsl
t_csl
Table 5.12 EEPROM Timing Values
DESCRIPTION
MIN
EECLK Cycle time
EECLK High time
EECLK Low time
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
EEDIO valid before rising edge of EECLK
(OUTPUT)
EEDIO disable after rising edge EECLK
(OUTPUT)
EEDIO setup to rising edge of EECLK (INPUT)
EEDIO hold after rising edge of EECLK
(INPUT)
EECLK low to data disable (OUTPUT)
EEDIO valid after EECS high (VERIFY)
EEDIO hold after EECS low (VERIFY)
EECS low
1110
550
550
1070
30
550
550
90
0
580
0
1070
TYP
MAX
1130
570
570
600
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Revision 1.6 (07-18-11)
166
DATASHEET
SMSC LAN9420/LAN9420i