LAN9420 Datasheet, PDF (50/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
3.4.3 Initialization
The following sequence explains the initialization steps for the DMA controller and activation of the
receive and transmit paths:
1. Configure the BUS_MODE register.
2. Mask unnecessary interrupts by writing to the DMAC_INTR_ENA register.
3. Software driver writes to descriptor base address registers RX_BASE_ADDR and
TX_BASE_ADDR after the RX and TX descriptor lists are created.
4. Write DMAC_CONTROL to set bits 13 (ST) and 1 (SR) to start the TX and RX DMA. The TX and
RX engines enter the running state and attempt to acquire descriptors from the respective
descriptor lists. The receive and transmit engines begin processing receive and transmit
operations.
5. Set bit 2 (RXEN) of MAC_CR to turn the receiver on.
6. Set bit 3 (TXEN) of MAC_CR to turn the transmitter on.
Note:
The TX and RX processes and paths are independent of each other and can be started or
stopped independently of one another. However, the control sequence required to activate the
RX path must be followed explicitly. The RX DMAC should be activated before the MAC’s
receiver. Failure to do so may lead to unpredictable results and untoward operation.
3.4.4 Transmit Operation
Transmission proceeds as follows:
1. The Host system sets up the Transmit Descriptor (TDES0-3) and sets the OWN bit (TDES0[31]).
2. Once set to the running state, the DMA controller reads the Host memory buffer to collect the first
descriptor. The starting address of the first descriptor is read from the TX_BASE_ADDR register.
3. Data transfer begins, and continues until the last DWORD of the frame is transferred. A frame may
traverse multiple descriptors. Frames must be delimited by the first segment (FS - TDES1[29]) and
last segment (LS - TDES1[30]) respectively.
4. When the frame transmission is completed, status is written into TDES0 with the OWN bit reset to
0. If the DMAC detects a descriptor flag that is owned by the Host, or if an error condition occurs,
the transmit engine enters into the suspended state and both (TU) Transmit Buffer Unavailable and
(NIS) Normal Interrupt Summary bits are set. Transmit Interrupt (TI) is set after completing
transmission of a frame that has an interrupt, and on completion the last descriptor (TDES0[30]) is
set. A new frame transmission will move the DMA from the Suspended state.
3.4.5 Receive Operation
The general sequence of events for reception of a frame is as follows:
1. The Host system sets up the receive descriptors RDES0-3 and sets the OWN bit (RDES0[31]). The
Host system polls the OWN bit and, once it recognizes a descriptor for itself, it can begin working
on the descriptor.
2. Once set to the running state, the DMA controller reads the Host memory buffer to collect the first
descriptor. The starting address of the first descriptor is read from the RX_BASE_ADDR register.
3. Data transfer begins, and continues until the last DWORD of the frame is transferred. A frame may
traverse multiple descriptors. The DMA controller delimits the frames by setting the First Segment
(RDES0[9]) and Last Segment (RDES0[8]) respectively. As a buffer is filled, or when the Last
Segment is transferred to the Host memory buffer, the descriptor of that buffer is closed (OWN bit
is cleared).
4. When a frame transfer is completed, the status field in RDES0 of the last descriptor is updated and
the OWN bit reset to 0, and the Receive Interrupt (RI) is then set. The receive engine continues
Revision 1.6 (07-18-11)
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DATASHEET
SMSC LAN9420/LAN9420i