LAN9420 Datasheet, PDF (89/171 Pages) SMSC Corporation – Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
4.2.2 Interrupt Control Register (INT_CTL)
Offset:
00C4h
Size:
32 bits
Interrupts are enabled/disabled through this register. Refer to Section 3.3.1, "Interrupt Controller," on
page 28 for more information on the Interrupt Controller.
Note: The DMAC interrupt (DMAC_INT) is enabled through the DCSR.
BITS
31:16
15
14
13
12
11:7
6:4
3
2
1
0
DESCRIPTION
RESERVED
Software Interrupt Enable (SW_INT_EN)
On a transition from low to high, this register bit triggers the software
interrupt.
RESERVED
Master Bus Error Interrupt Enable (MBERR_INT_EN)
When set high, the Master Bus Error is enabled to generate an interrupt.
Slave Bus Error Interrupt Enable (SBERR_INT_EN)
When set high, the Slave Bus Error is enabled to generate an interrupt.
RESERVED
GPIO [2:0] (GPIOx_INT_EN)
When set high the GPIOx are enabled as interrupt sources.
GP Timer Interrupt Enable (GPT_INT_EN)
When set high the General Purpose Timer is enabled as an interrupt
source.
PHY Interrupt Enable (PHY_INT_EN)
When set high, the PHY interrupt is enabled as an interrupt source.
Wake Event Interrupt Enable (WAKE_INT_EN)
When set high, wake event detection is enabled as an interrupt source.
RESERVED
TYPE
RO
R/W
DEFAULT
-
0b
RO
-
R/W
0b
R/W
0b
RO
-
R/W
000b
R/W
0b
R/W
0b
R/W
0b
RO
-
SMSC LAN9420/LAN9420i
89
DATASHEET
Revision 1.6 (07-18-11)